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prasad.sn.sn@gmail.com
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Research& Development
LIST OF JOURNAL PUBLICATIONS

Low power adder based ANN

S.N.Prasad,S.Y.Kulkarni.,”Low power adder based ANN”,International Journal of Computer Applications(0975-8887),Volume-118-No.10,May 2015.

Low power datapath architecture for ANN

S.N.Prasad,S.Y.Kulkarni,”Low power datapath architecture for ANN”, International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 18 (2015) pp 38785-38789-Scopus indexed.

The Optimized datapath ANN for Low power and Embedded applications

S.N.Prasad,S.Y.Kulkarni,” The Optimized datapath ANN for Low power and Embedded applications”-Applied to International Journal for Engineering and Technology(IJET)-A scopus indexed journal.

A Survey on Interference free allocation of spectrum For Military applications using propogation models for LTE

Priyanka N.,S.N.Prasad,” A Survey on Interference free allocation of spectrum For Military applications using propogation models for LTE”, IJTRE (International Journal For Technological Research InEngineering), Volume 2, Issue 7, March - 2015.

Review On Error Correcting Smart Reliable Network-on-Chip

Gunashree P,S.N.Prasad,” Review On Error Correcting Smart Reliable Network- on-Chip”,International Journal of Research and Development Organization,ISSN-3967-0867

A Comprehensive study of guided filter and its applications in Computer vision and graphics.

Akash R,S.N.Prasad,”A Comprehensive study of guided filter and its applications in Computer vision and graphics.”,International Journal for Technological Research in Engineering,Volume-2,Issue 9-May2015,ISSN(online)-2347-4718.

List Of Conference Publications

Shruthi G, Prasad S N, “IMPLEMENTATION OF PHASE LOCKED LOOP IN DEEP SUBMICRON TECHNOLOGY”. 2 nd International Conference on recent trends in Signal processing, Image processing and VLSI (ICrtSIV), 2015 organised by Dept. of ECE, Don Bosco Institute of Technology.
Gunashree P,S.N.Prasad,” Review On Error Correcting Smart Reliable Network-on-Chip, 2 nd International Conference on recent trends in Signal processing, Image processing and VLSI (ICrtSIV), 2015 organised by Dept. of ECE, Don Bosco Institute of Technology.
Design of error correcting smart reliable NoC at RVCE-ICTIS-2015.
Implementation of PLL in a deep submicron technology at International Conference on recent trends in Signal Processing,Image Processing and VLSI BY Reseach Publishing Services.
Design of Error Tolerant Adder in VLSI applications at BMSCE.
FPGA Implementation of Connection oriented Parallel Switching Networks at BMSCE.
Design of Industrial Atmospheric Environment monitoring system based on ARM 7 platform and 3G Technology.
VLSI Design and Implementation of High speed upsampler using Multirate Technique.
FPGA based Architecture of a Telecommand SoC for transfer of signals from Ground station to Spacecraft.

Papers Presented and Journal Publications

Before joining REVA University